This application claims the priority of Korean Patent Application No. 2002-38890, filed on 5 Jul. 2002, in the Korean Intellectual Property Office, the contents of which are incorporated herein in their entirety by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor device having an output driver capable of preventing distortion of output data when the semiconductor device performs a high frequency operation.
2. Description of the Related Art
Presently, semiconductor memory devices must be highly integrated and capable of performing operations quickly. In line with this, a newly developed memory that can transmit a considerable amount of data at a high speed while consuming low power is required. A double data rate dynamic random access memory (DDR DRAM) or a rambus DRAM having a higher operating speed than a synchronous DRAM (SDRAM) having a maximum operating speed of 100-200 MHz is expected to become popular.
FIG. 1 is a block diagram of a semiconductor memory device 100 having a conventional output driver, and FIG. 2 is a waveform diagram of an output wave of the output driver of FIG. 1.
Referring to FIG. 1, a semiconductor memory device 100 includes an output driver 110, a first driving circuit 120, and a second driving circuit 130. In the output driver 110, a first NMOS transistor N1 and a second NMOS transistor N2 are connected in series. A drain of the first NMOS transistor N1 is connected to an output pad DQ, and a source of the second NMOS transistor N2 is connected to a ground voltage VSS.
When data DATA is read, the first NMOS transistor N1 is turned on in response to a gate voltage VGATE. A gate Q of the second NMOS transistor N2 is turned on or off in response to a data voltage VEXT which is at the level of an external voltage EVCC.
The first driving circuit 120 receives a reference voltage REFV to generate the gate voltage VGATE. The second driving circuit 130 receives data DATA and the external voltage EVCC to generate the data voltage VEXT.
If data DATA is at a high level, the data voltage VEXT is generated at a high level, and thus the second NMOS transistor N2 is turned on. The output pad DQ outputs data DATA at a low level.
If data DATA is at a low level, the data voltage VEXT is generated at a low level, and thus the second NMOS transistor N2 is turned off. The output pad DQ outputs data DATA at a high level.
In general, the rambus DRAM has a high operating speed of 800 Mbps. However, when the rambus DRAM operates at a high speed over 800 Mbps, skew occurs in data DATA which is output to the output pad DQ.
A waveform of the gate voltage VEXT which is applied to the gate Q of the second NMOS transistor N2 is illustrated in FIG. 2(A).
Since the second NMOS transistor N2 is large in size, the load on the gate Q is great, and thus the data voltage VEXT is not capable of performing a full swing. In particular, the data voltage VEXT is not capable of performing the full swing more frequently when the data voltage VEXT changes between the low level and the high level than when the data voltage VEXT continues at the high level.
As shown in FIG. 2(A), the swing of the data voltage VEXT decreases by about 240 mV when the data voltage VEXT of the gate Q changes between the low level and the high level in comparison to the case in which the data voltage VEXT of the gate Q continues at the high level.
Due to the decrease in the swing as described above, a delay of about 57 ps for output of the output pad DQ occurs as shown in FIG. 2(B). As a result, margin of setup time or hold time based on an external clock signal decreases in the output of the rambus DRAM.
FIG. 3 is a timing diagram showing the relationship between a reference clock signal CTM of the rambus DRAM and data DATA. As a system operates at a high speed and a high operating frequency, a time specification of output data becomes tight. The data DATA sensed from a cell of the rambus DRAM is output such that its center is synchronized with a rising edge or a falling edge of the reference clock signal CTM.
The time from the rising edge or the falling edge of the reference clock signal CTM to the front of the data DATA is denoted as TQMAX, and the time from the rising edge or the falling edge of the reference clock signal CTM to the back of the data DATA is denoted as TQMIN. TQMAX and TQMIN are important specifications representing the output characteristics of the rambus DRAM.
FIG. 4 is a circuit diagram of an output driver circuit of the rambus DRAM. FIG. 5 is a waveform diagram illustrating a read operation of the output driver circuit of FIG. 4. FIG. 6 is a timing diagram showing a delay of data due to a rise in a voltage of a connection node of FIG. 4.
Referring FIG. 4, an output driver circuit 400 of the rambus DRAM includes a driver portion 410 having NMOS transistors N1 and N2, which are connected in series, an output pad DQ, and a precharge transistor 420.
In FIG. 4, a termination voltage VTERM and a termination resistor RTERM outside of a chip (not shown) where the output driver circuit 400 is mounted are shown.
Hereinafter, the operation of the output driver circuit 400 of the rambus DRAM will be described with reference to FIG. 4. When the data DATA is read, a first gate voltage VGATE is applied to the gate of the first NMOS transistor N1 of the driver portion 410 to turn on the first NMOS transistor N1. The first gate voltage VGATE is lower than the operating voltage of the device.
When the data DATA is not read, the first gate voltage VGATE is applied to the first NMOS transistor N1, and the first NMOS transistor N1 is turned on. Therefore, the capacitance of the driver portion 410 when the output pad DQ is viewed from outside increases, and thus a signal transmitted from another device may be distorted. Accordingly, the first gate voltage VGATE is required to be applied only when the data DATA is read.
The data DATA sensed from a DRAM core is applied to the gate Q of the second NMOS transistor N2. If the data DATA applied to the gate Q of the second NMOS transistor N2 is at a high level, the second NMOS transistor N2 is turned on and the data DATA at a low level is output through the output pad DQ.
The precharge transistor 420 precharges a connection node A of the first NMOS transistor N1 and the second NMOS transistor N2 to a level of a threshold voltage of the first gate voltage VGATE of the first NMOS transistor N1, so as to prevent the first NMOS transistor N1 from being turned on when the data DATA is not read.
Referring to FIG. 5, when the data DATA is read, the voltage level of the first gate voltage VGATE is raised from 0 V to the high level. The second gate voltage PVGATE, which is at a high level to precharge the connection node A, falls to a low level.
When the first gate voltage VGATE is raised from the low level to the high level, a charge coupling occurs in the connection node A due to the gate of the first NMOS transistor N1 to junction overlap. Therefore, the voltage level of the connection node A is raised by 100 mV, as shown in FIG. 5.
The rise in the voltage level of the connection node A decreases TQMAX by 13 ps when the data DATA is output to the output pad DQ at the high level.
If during a process the applied voltage, the temperature, or the like of the device is changed and thus the raised voltage of the connection node A increases, the delay in outputting first data at a high level through the output pad DQ will also increase.